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Espressif Systems /ESP32-P4 /PARL_IO /TX_DATA_CFG

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Interpret as TX_DATA_CFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TX_BITLEN0 (TX_DATA_ORDER_INV)TX_DATA_ORDER_INV 0TX_BUS_WID_SEL

Description

Parallel TX data configuration register.

Fields

TX_BITLEN

Configures expected byte number of sent data.
TX_DATA_ORDER_INV

Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
TX_BUS_WID_SEL

Configures the txd bus width. 3’d0: bus width is 1. 3’d1: bus width is 2. 3’d2: bus width is 4. 3’d3: bus width is 8.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data